Among ADCs, which sample and digitize an analog signal, SAR type ADCs and flash type ADCs are well known in the art.
The SAR ADC generates digital bits by successively comparing an analog input signal per one clock cycle. The digital bits of the analog input signal can be obtained by comparing the bits in the order from the most significant bit to the least significant bit. However, the SAR ADC can obtain only one bit per one clock cycle as shown in FIG. 1. Therefore, it is difficult to realize a fast operation.
The flash ADC obtains the digital bits of the analog input signal by comparing the analog input signal with various reference levels at one time by using multiple comparators. Since, however, the flash ADC compares the signal with various reference levels in one step, the number of comparators and DACs required for constructing the flash ADC is exponentially increased as the number of digital bits to be obtained in one step is increased. Accordingly, the cost is increased and the size is also increased.